FIG. 1 is a schematic diagram of a five-stage Clos switching network 10.
In the pictured embodiment, there are 144 space inputs, one to each time switch slice 12 of stage 1. Each space input has 48 timeslots, illustrated as separate parallel inputs to the time switch slices 12, for a total of 6,912 input timeslots. Similarly, there are 6,912 output timeslots.
Stages 1, 3 and 5 are timeslot interchange stages. Each of these stages has 144 time switch slices 12, each of which has 48 inputs and 48 outputs. Stages 2 and 4 are space switch stages. Each has 48 space switch slices 14 and each space switch slice 14 has 144 inputs and 144 outputs.
In stage 1, the 48 time slots for each of the 144 inputs are rearranged, and perhaps duplicated, and forwarded to appropriate ones of the space switches in stage 2. Specifically, data placed in timeslot [0] at each time switch slice 12 is forwarded to switch 14[0] in stage 2. All timeslots [1] are forwarded to switch 14[1], and so on.
In stage 2, space switch slice 14[0] directs each of the 144 [0] timeslots to an appropriate one of 144 time switch slices in stage 3, space switch slice 14[1] directs all of the [1] timeslots, and so on.
Subsequent stages perform similarly. For simplicity, only representative interconnects between switch stages are shown.
Stages 1 and 2 operate together as a concentrator. Stage 3 performs copy distribution. Stage 3, 4 and 5 function collectively as a rearrangeably non-blocking unicast Clos network. A unicast hardware scheduler arranges all connection calls from input timeslots to output timeslots.